1. Field of the Invention
The present invention relates to a computer system using a bus bridge(s) to interface a central processor(s), an accelerated graphics port (AGP) video graphics processor(s), main memory and input-output peripherals together, and more particularly, to merging AGP transaction read requests that are within a cacheline of main memory addresses being accessed.
2. Description of the Related Technology
A computer system has a plurality of information buses (used for transferring instructions, data and addresses) such as a host bus, a memory bus, high speed expansion buses such as an Accelerated Graphics Port (AGP) bus and a Peripheral Component Interconnect (PCI) bus, and other peripheral buses such as the Small Computer System Interface (SCSI), Extension to Industry Standard Architecture (EISA), and Industry Standard Architecture (ISA). The processor(s) of the computer system communicates with main memory and with the peripherals that make up the computer system over these various buses.
Increasingly inexpensive but sophisticated processors, such as microprocessors, have revolutionized the role of computer systems, such as personal computers by enabling complex applications software to run at mainframe computer speeds. The latest microprocessors have brought the level of technical sophistication to personal computers that, just a few years ago, was available only in mainframe and mini-computer systems. Some representative examples of these new microprocessors are the "PENTIUM" and "PENTIUM PRO" (registered trademarks of Intel Corporation). Advanced microprocessors are also manufactured by Advanced Micro Devices, Cyrix, IBM, Digital Equipment Corp., Sun Microsystems and Motorola.
These sophisticated microprocessors have, in turn, made possible running complex application programs using advanced three dimensional ("3-D") graphics for computer aided drafting and manufacturing, engineering simulations, games and the like. Increasingly complex 3-D graphics require higher speed access to ever larger amounts of graphics information stored in memory. This memory may be part of the video graphics processor system, but, preferably, would be best (lowest cost) if part of the main computer system memory because shifting graphics information from local graphics memory to main memory significantly reduces computer system costs when implementing 3-D graphics. Intel Corporation has proposed a low cost but improved 3-D graphics standard called the "Accelerated Graphics Port" (AGP) initiative. With AGP 3-D, graphics data, in particular textures, may be shifted out of the graphics controller local memory to computer system main memory. The computer system main memory is lower in cost than the graphics controller local memory and is more easily adapted for a multitude of other uses besides storing graphics data.
The proposed Intel AGP 3-D graphics standard defines a high speed data pipeline, or "AGP bus," between the graphics controller and system main memory. This AGP bus has sufficient bandwidth for the graphics controller to retrieve textures from system memory without materially affecting computer system performance for other non-graphics operations. The Intel 3-D graphics standard is a specification which provides signal, protocol, electrical, and mechanical specifications for the AGP bus and devices attached thereto. This specification is entitled "Accelerated Graphics Port Interface Specification Revision 1.0," dated Jul. 31, 1996, the disclosure of which is hereby incorporated by reference. This AGP Specification is available from Intel Corporation, Santa Clara, Calif.
The computer system main memory, typically, may be comprised of fast access synchronous dynamic random access memory (SDRAM). The memory control and interface logic for the SDRAM may be optimized for reading and/or writing a desired number of bytes of information for each memory transaction. A desired number of bytes of information may be, for example, 32 bytes, and may be referred to hereinafter as a "cacheline" or "data paragraph." The number of bytes comprising the cacheline or data paragraph may be optimized for the SDRAM and processor of the computer system, however, peripheral devices such an AGP video controller may not request a memory transaction which is a full cacheline or even aligned on a cacheline address boundary (e.g., 32 byte aligned). An AGP bus agent (e.g., the AGP video graphics controller) requesting a read transaction of less than a full cacheline, may reduce the efficiency of the memory control and interface logic in processing the AGP bus transactions because an increased number of main memory accesses may be required to retire these sub-cacheline AGP read transactions.
What is needed to more fully and efficiently utilize the computer system and its main memory is a system, method and apparatus for merging AGP read transaction requests from an AGP device to the main memory that are less than a full cacheline in size or are not cacheline address aligned.